1. Field of the Invention
The present invention is generally directed to the field of testing integrated circuit devices, and, more particularly, to a probe card with integrated light conditioning devices for testing imaging devices, and methods of fabricating same.
2. Description of the Related Art
The microelectronics industry is highly competitive and microelectronic device manufacturers are very sensitive to quality and cost considerations. Most microelectronic device manufacturers are required to test the performance of each microelectronic device prior to shipping it to a customer. For example, microelectronic imagers are commonly tested by establishing temporary electrical connections between a test system and electrical contacts on each microelectronic imaging die while simultaneously exposing an image sensor on the device to light.
One way of establishing a temporary electrical connection between the test system and the contacts on a microelectronic component employs a probe card carrying a plurality of probe pins. The probe pins are typically either a length of wire (e.g., cantilevered wire probes) or a relatively complex spring-biased mechanism (e.g., pogo pins). The probe pins are connected to the probe card and arranged in a predetermined array for use with a specific microelectronic component configuration. For example, when testing a microelectronic imager with a conventional probe card (whether it be a cantilevered wire probe card, a pogo pin probe card or another design), the probe card is positioned proximate to the front side of the imaging die to be tested. The probe card and the imaging die are aligned with each other in an effort to precisely align each of the probe pins of the probe card with a corresponding electrical contact of the front side of the imaging die.
One problem with testing imaging dies at the wafer level is that it is difficult to expose an image sensor to light while simultaneously aligning the probe pins or the body of the probe card with the corresponding electrical contacts on the front side of the imaging die. For example, because the probe card is positioned over the image sensor to contact the front side bond-pads on the die, the probe card must have a plurality of holes or apertures through which light can pass. This limits wafer-level testing methods because of the physical constraints of probe card structures and the limited testing area available on the wafer. Further, the probe card and/or probe pins positioned proximate (but not over) the image sensor may also interfere with the light directed to the image sensor (e.g., shadowing, reflections). These limitations result in the ability to test only a fraction of the imaging dies on a wafer of imaging dies as compared to the number of other types of dies that can be tested in non-imaging applications (e.g., memory, processors, etc.). Typically, only four CMOS imaging dies can be tested simultaneously on a wafer, compared to 128 DRAM dies using the same equipment. Accordingly, there is a need to improve the efficiency and throughput for testing imaging dies.
Traditional probe card structures for testing imaging devices are manufactured by a process employed in manufacturing printed circuit boards. The light openings formed in such traditional probe card structures are formed by traditional mechanical means, such as drilling. As imager devices become more sophisticated, the traditional structure of such probe cards can be a disadvantage as it relates to testing of advanced imager devices. Moreover, the prior art probe cards may limit their effectiveness or efficiency as it relates to future device generations, as such devices continue to be reduced in size.
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.